From Python to Silicon!

Design hardware with Python

MyHDL turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem.

Integrates seamlessly

MyHDL designs can be converted to Verilog or VHDL automatically, and implemented using a standard tool flow.

Silicon proven

Many MyHDL designs have been implemented in ASICs and FPGAs, including some high volume applications.

Open source

MyHDL is an open source, pure Python package. Install with pip and enjoy the Python ecosystem immediately. Visit the project on Github.

Release news

31-May-2019  MyHDL 0.11.0 released

General news

18-Mar-2015  Python3 Support

18-Mar-2014  A makeover for

24-Apr-2013  Follow MyHDL on twitter!