====== CPLD Fitter Report ====== cpldfit: version I.26 Xilinx Inc. Fitter Report Design Name: StopWatch Date: 3-12-2006, 10:56PM Device Used: XC2C64A-5-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 36 /64 ( 56%) 54 /224 ( 24%) 36 /160 ( 22%) 35 /64 ( 55%) 24 /33 ( 73%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 13/40 21/56 3/ 8 0/1 0/1 0/1 0/1 FB2 10/16 11/40 15/56 8/ 9 0/1 0/1 0/1 0/1 FB3 9/16 8/40 16/56 9/ 9* 0/1 0/1 0/1 0/1 FB4 1/16 4/40 2/56 1/ 7 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 36/64 36/160 54/224 21/33 0/4 0/4 0/4 0/4 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 1/3 1/1 0/4 Signal 'clock' mapped onto global clock net GCK0. Signal 'reset' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 1 1 | I/O : 19 25 Output : 21 21 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 1 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 24 24 End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 21 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State ones_led<2> 1 4 FB1_2 43 I/O O LVCMOS18 FAST DFF RESET ones_led<5> 3 4 FB1_3 42 I/O O LVCMOS18 FAST DFF RESET ones_led<0> 2 4 FB1_9 40 GTS/I/O O LVCMOS18 FAST DFF RESET tens_led<2> 1 4 FB2_1 1 I/O O LVCMOS18 FAST DFF RESET tens_led<0> 2 4 FB2_2 2 I/O O LVCMOS18 FAST DFF RESET tens_led<3> 3 4 FB2_5 3 I/O O LVCMOS18 FAST DFF RESET tens_led<6> 2 4 FB2_6 4 I/O O LVCMOS18 FAST DFF RESET tens_led<1> 2 4 FB2_8 6 GCK/I/O O LVCMOS18 FAST DFF RESET tens_led<4> 2 4 FB2_10 7 GCK/I/O O LVCMOS18 FAST DFF RESET tens_led<5> 3 4 FB2_12 8 I/O O LVCMOS18 FAST DFF RESET tenths_led<2> 1 4 FB2_13 9 I/O O LVCMOS18 FAST DFF RESET ones_led<3> 3 4 FB3_1 35 I/O O LVCMOS18 FAST DFF RESET ones_led<6> 2 4 FB3_2 34 I/O O LVCMOS18 FAST DFF RESET ones_led<1> 2 4 FB3_3 33 I/O O LVCMOS18 FAST DFF RESET ones_led<4> 2 4 FB3_6 29 I/O O LVCMOS18 FAST DFF RESET tenths_led<0> 2 4 FB3_10 28 I/O O LVCMOS18 FAST DFF RESET tenths_led<3> 3 4 FB3_11 27 I/O O LVCMOS18 FAST DFF RESET tenths_led<6> 2 4 FB3_12 26 I/O O LVCMOS18 FAST DFF RESET tenths_led<5> 3 4 FB3_14 25 I/O O LVCMOS18 FAST DFF RESET tenths_led<1> 2 4 FB3_15 24 I/O O LVCMOS18 FAST DFF RESET tenths_led<4> 2 4 FB4_1 11 I/O O LVCMOS18 FAST DFF RESET ** 15 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State _StopWatch_timecount_inst_logic_seen 0 0 FB1_1 DFF RESET ones<0> 1 5 FB1_4 TFF RESET ones<2> 1 7 FB1_5 TFF RESET tens<1> 3 13 FB1_6 TFF RESET tens<2> 2 13 FB1_7 TFF RESET tens<3> 1 12 FB1_8 TFF RESET tenths<0> 1 1 FB1_10 TFF RESET tenths<2> 1 3 FB1_11 TFF RESET tenths<1> 3 5 FB1_12 TFF RESET tenths<3> 2 5 FB1_13 TFF RESET ones<1> 3 9 FB1_14 TFF RESET ones<3> 2 9 FB1_15 TFF RESET tens<0> 1 9 FB1_16 TFF RESET N_PZ_215 2 3 FB2_15 _StopWatch_timecount_inst_logic_counting 1 2 FB2_16 TFF RESET ** 3 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style startstop FB1_1 44 I/O I LVCMOS18 KPR reset FB1_13 36 GSR/I/O GSR LVCMOS18 KPR clock FB2_7 5 GCK/I/O GCK LVCMOS18 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 13/27 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 21/35 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use _StopWatch_timecount_inst_logic_seen 0 FB1_1 44 I/O I ones_led<2> 1 FB1_2 43 I/O O ones_led<5> 3 FB1_3 42 I/O O ones<0> 1 FB1_4 (b) (b) ones<2> 1 FB1_5 (b) (b) tens<1> 3 FB1_6 (b) (b) tens<2> 2 FB1_7 (b) (b) tens<3> 1 FB1_8 (b) (b) ones_led<0> 2 FB1_9 40 GTS/I/O O tenths<0> 1 FB1_10 39 GTS/I/O (b) tenths<2> 1 FB1_11 38 GTS/I/O (b) tenths<1> 3 FB1_12 37 GTS/I/O (b) tenths<3> 2 FB1_13 36 GSR/I/O GSR ones<1> 3 FB1_14 (b) (b) ones<3> 2 FB1_15 (b) (b) tens<0> 1 FB1_16 (b) (b) Signals Used by Logic in Function Block 1: N_PZ_215 6: tens<0> 10: tenths<0> 2: ones<0> 7: tens<1> 11: tenths<1> 3: ones<1> 8: tens<2> 12: tenths<2> 4: ones<2> 9: tens<3> 13: tenths<3> 5: ones<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ones_led<2> .XXXX................................... 4 ones_led<5> .XXXX................................... 4 ones<0> X........XXXX........................... 5 ones<2> XXX......XXXX........................... 7 tens<1> XXXXXXXXXXXXX........................... 13 tens<2> XXXXXXXXXXXXX........................... 13 tens<3> XXXXXXXX.XXXX........................... 12 ones_led<0> .XXXX................................... 4 tenths<0> X....................................... 1 tenths<2> X........XX............................. 3 tenths<1> X........XXXX........................... 5 tenths<3> X........XXXX........................... 5 ones<1> XXXXX....XXXX........................... 9 ones<3> XXXXX....XXXX........................... 9 tens<0> XXXXX....XXXX........................... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 11/29 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 15/41 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use tens_led<2> 1 FB2_1 1 I/O O tens_led<0> 2 FB2_2 2 I/O O (unused) 0 FB2_3 (b) (unused) 0 FB2_4 (b) tens_led<3> 3 FB2_5 3 I/O O tens_led<6> 2 FB2_6 4 I/O O (unused) 0 FB2_7 5 GCK/I/O GCK tens_led<1> 2 FB2_8 6 GCK/I/O O (unused) 0 FB2_9 (b) tens_led<4> 2 FB2_10 7 GCK/I/O O (unused) 0 FB2_11 (b) tens_led<5> 3 FB2_12 8 I/O O tenths_led<2> 1 FB2_13 9 I/O O (unused) 0 FB2_14 (b) N_PZ_215 2 FB2_15 (b) (b) _StopWatch_timecount_inst_logic_counting 1 FB2_16 (b) (b) Signals Used by Logic in Function Block 1: _StopWatch_timecount_inst_logic_counting 5: tens<1> 9: tenths<1> 2: _StopWatch_timecount_inst_logic_seen 6: tens<2> 10: tenths<2> 3: startstop 7: tens<3> 11: tenths<3> 4: tens<0> 8: tenths<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs tens_led<2> ...XXXX................................. 4 tens_led<0> ...XXXX................................. 4 tens_led<3> ...XXXX................................. 4 tens_led<6> ...XXXX................................. 4 tens_led<1> ...XXXX................................. 4 tens_led<4> ...XXXX................................. 4 tens_led<5> ...XXXX................................. 4 tenths_led<2> .......XXXX............................. 4 N_PZ_215 XXX..................................... 3 _StopWatch_timecount_inst_logic_counting .XX..................................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 8/32 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 16/40 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use ones_led<3> 3 FB3_1 35 I/O O ones_led<6> 2 FB3_2 34 I/O O ones_led<1> 2 FB3_3 33 I/O O (unused) 0 FB3_4 (b) (unused) 0 FB3_5 (b) ones_led<4> 2 FB3_6 29 I/O O (unused) 0 FB3_7 (b) (unused) 0 FB3_8 (b) (unused) 0 FB3_9 (b) tenths_led<0> 2 FB3_10 28 I/O O tenths_led<3> 3 FB3_11 27 I/O O tenths_led<6> 2 FB3_12 26 I/O O (unused) 0 FB3_13 (b) tenths_led<5> 3 FB3_14 25 I/O O tenths_led<1> 2 FB3_15 24 I/O O (unused) 0 FB3_16 (b) Signals Used by Logic in Function Block 1: ones<0> 4: ones<3> 7: tenths<2> 2: ones<1> 5: tenths<0> 8: tenths<3> 3: ones<2> 6: tenths<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ones_led<3> XXXX.................................... 4 ones_led<6> XXXX.................................... 4 ones_led<1> XXXX.................................... 4 ones_led<4> XXXX.................................... 4 tenths_led<0> ....XXXX................................ 4 tenths_led<3> ....XXXX................................ 4 tenths_led<6> ....XXXX................................ 4 tenths_led<5> ....XXXX................................ 4 tenths_led<1> ....XXXX................................ 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 4/36 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use tenths_led<4> 2 FB4_1 11 I/O O (unused) 0 FB4_2 12 I/O (unused) 0 FB4_3 (b) (unused) 0 FB4_4 (b) (unused) 0 FB4_5 (b) (unused) 0 FB4_6 (b) (unused) 0 FB4_7 14 I/O (unused) 0 FB4_8 (b) (unused) 0 FB4_9 (b) (unused) 0 FB4_10 (b) (unused) 0 FB4_11 18 I/O (unused) 0 FB4_12 (b) (unused) 0 FB4_13 19 I/O (unused) 0 FB4_14 20 I/O (unused) 0 FB4_15 22 I/O (unused) 0 FB4_16 (b) Signals Used by Logic in Function Block 1: tenths<0> 3: tenths<2> 4: tenths<3> 2: tenths<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs tenths_led<4> XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** N_PZ_215 <= NOT _StopWatch_timecount_inst_logic_counting XOR (startstop AND NOT _StopWatch_timecount_inst_logic_seen); FTCPE__StopWatch_timecount_inst_logic_counting: FTCPE port map (_StopWatch_timecount_inst_logic_counting,_StopWatch_timecount_inst_logic_counting_T,clock,reset,'0','1'); _StopWatch_timecount_inst_logic_counting_T <= (startstop AND NOT _StopWatch_timecount_inst_logic_seen); FDCPE__StopWatch_timecount_inst_logic_seen: FDCPE port map (_StopWatch_timecount_inst_logic_seen,startstop,clock,reset,'0','1'); FTCPE_ones0: FTCPE port map (ones(0),ones_T(0),clock,reset,'0','1'); ones_T(0) <= (NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3)); FTCPE_ones1: FTCPE port map (ones(1),ones_T(1),clock,reset,'0','1'); ones_T(1) <= ((ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0)) OR (NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND ones(2)) OR (NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(3))); FTCPE_ones2: FTCPE port map (ones(2),ones_T(2),clock,reset,'0','1'); ones_T(2) <= (ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0)); FTCPE_ones3: FTCPE port map (ones(3),ones_T(3),clock,reset,'0','1'); ones_T(3) <= ((ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND ones(2)) OR (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3))); FDCPE_ones_led0: FDCPE port map (ones_led(0),ones_led_D(0),clock,'0','0','1'); ones_led_D(0) <= ((NOT ones(1) AND ones(0) AND NOT ones(2) AND NOT ones(3)) OR (NOT ones(1) AND NOT ones(0) AND ones(2) AND NOT ones(3))); FDCPE_ones_led1: FDCPE port map (ones_led(1),ones_led_D(1),clock,'0','0','1'); ones_led_D(1) <= ((ones(1) AND NOT ones(0) AND ones(2) AND NOT ones(3)) OR (NOT ones(1) AND ones(0) AND ones(2) AND NOT ones(3))); FDCPE_ones_led2: FDCPE port map (ones_led(2),ones_led_D(2),clock,'0','0','1'); ones_led_D(2) <= (ones(1) AND NOT ones(0) AND NOT ones(2) AND NOT ones(3)); FDCPE_ones_led3: FDCPE port map (ones_led(3),ones_led_D(3),clock,'0','0','1'); ones_led_D(3) <= ((ones(1) AND ones(0) AND ones(2) AND NOT ones(3)) OR (NOT ones(1) AND ones(0) AND NOT ones(2) AND NOT ones(3)) OR (NOT ones(1) AND NOT ones(0) AND ones(2) AND NOT ones(3))); FDCPE_ones_led4: FDCPE port map (ones_led(4),ones_led_D(4),clock,'0','0','1'); ones_led_D(4) <= NOT (((ones(1) AND NOT ones(0) AND NOT ones(3)) OR (NOT ones(1) AND NOT ones(0) AND NOT ones(2)))); FDCPE_ones_led5: FDCPE port map (ones_led(5),ones_led_D(5),clock,'0','0','1'); ones_led_D(5) <= ((ones(1) AND ones(0) AND NOT ones(3)) OR (ones(1) AND NOT ones(0) AND NOT ones(2) AND NOT ones(3)) OR (NOT ones(1) AND ones(0) AND NOT ones(2) AND NOT ones(3))); FDCPE_ones_led6: FDCPE port map (ones_led(6),ones_led_D(6),clock,'0','0','1'); ones_led_D(6) <= ((NOT ones(1) AND NOT ones(2) AND NOT ones(3)) OR (ones(1) AND ones(0) AND ones(2) AND NOT ones(3))); FTCPE_tens0: FTCPE port map (tens(0),tens_T(0),clock,reset,'0','1'); tens_T(0) <= (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3)); FTCPE_tens1: FTCPE port map (tens(1),tens_T(1),clock,reset,'0','1'); tens_T(1) <= ((NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(1) AND tens(0)) OR (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(0) AND NOT tens(2)) OR (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(0) AND tens(3))); FTCPE_tens2: FTCPE port map (tens(2),tens_T(2),clock,reset,'0','1'); tens_T(2) <= ((NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(1) AND tens(0)) OR (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(0) AND tens(2) AND NOT tens(3))); FTCPE_tens3: FTCPE port map (tens(3),tens_T(3),clock,reset,'0','1'); tens_T(3) <= (NOT ones(1) AND NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3) AND ones(0) AND NOT ones(2) AND ones(3) AND tens(1) AND tens(0) AND tens(2)); FDCPE_tens_led0: FDCPE port map (tens_led(0),tens_led_D(0),clock,'0','0','1'); tens_led_D(0) <= ((NOT tens(1) AND tens(0) AND NOT tens(2) AND NOT tens(3)) OR (NOT tens(1) AND NOT tens(0) AND tens(2) AND NOT tens(3))); FDCPE_tens_led1: FDCPE port map (tens_led(1),tens_led_D(1),clock,'0','0','1'); tens_led_D(1) <= ((tens(1) AND NOT tens(0) AND tens(2) AND NOT tens(3)) OR (NOT tens(1) AND tens(0) AND tens(2) AND NOT tens(3))); FDCPE_tens_led2: FDCPE port map (tens_led(2),tens_led_D(2),clock,'0','0','1'); tens_led_D(2) <= (tens(1) AND NOT tens(0) AND NOT tens(2) AND NOT tens(3)); FDCPE_tens_led3: FDCPE port map (tens_led(3),tens_led_D(3),clock,'0','0','1'); tens_led_D(3) <= ((tens(1) AND tens(0) AND tens(2) AND NOT tens(3)) OR (NOT tens(1) AND tens(0) AND NOT tens(2) AND NOT tens(3)) OR (NOT tens(1) AND NOT tens(0) AND tens(2) AND NOT tens(3))); FDCPE_tens_led4: FDCPE port map (tens_led(4),tens_led_D(4),clock,'0','0','1'); tens_led_D(4) <= NOT (((tens(1) AND NOT tens(0) AND NOT tens(3)) OR (NOT tens(1) AND NOT tens(0) AND NOT tens(2)))); FDCPE_tens_led5: FDCPE port map (tens_led(5),tens_led_D(5),clock,'0','0','1'); tens_led_D(5) <= ((tens(1) AND tens(0) AND NOT tens(3)) OR (tens(1) AND NOT tens(2) AND NOT tens(3)) OR (tens(0) AND NOT tens(2) AND NOT tens(3))); FDCPE_tens_led6: FDCPE port map (tens_led(6),tens_led_D(6),clock,'0','0','1'); tens_led_D(6) <= ((NOT tens(1) AND NOT tens(2) AND NOT tens(3)) OR (tens(1) AND tens(0) AND tens(2) AND NOT tens(3))); FTCPE_tenths0: FTCPE port map (tenths(0),NOT N_PZ_215,clock,reset,'0','1'); FTCPE_tenths1: FTCPE port map (tenths(1),tenths_T(1),clock,reset,'0','1'); tenths_T(1) <= NOT (((NOT tenths(0)) OR (N_PZ_215) OR (NOT tenths(1) AND NOT tenths(2) AND tenths(3)))); FTCPE_tenths2: FTCPE port map (tenths(2),tenths_T(2),clock,reset,'0','1'); tenths_T(2) <= (tenths(1) AND tenths(0) AND NOT N_PZ_215); FTCPE_tenths3: FTCPE port map (tenths(3),tenths_T(3),clock,reset,'0','1'); tenths_T(3) <= ((tenths(1) AND tenths(0) AND NOT N_PZ_215 AND tenths(2)) OR (NOT tenths(1) AND tenths(0) AND NOT N_PZ_215 AND NOT tenths(2) AND tenths(3))); FDCPE_tenths_led0: FDCPE port map (tenths_led(0),tenths_led_D(0),clock,'0','0','1'); tenths_led_D(0) <= ((NOT tenths(1) AND tenths(0) AND NOT tenths(2) AND NOT tenths(3)) OR (NOT tenths(1) AND NOT tenths(0) AND tenths(2) AND NOT tenths(3))); FDCPE_tenths_led1: FDCPE port map (tenths_led(1),tenths_led_D(1),clock,'0','0','1'); tenths_led_D(1) <= ((tenths(1) AND NOT tenths(0) AND tenths(2) AND NOT tenths(3)) OR (NOT tenths(1) AND tenths(0) AND tenths(2) AND NOT tenths(3))); FDCPE_tenths_led2: FDCPE port map (tenths_led(2),tenths_led_D(2),clock,'0','0','1'); tenths_led_D(2) <= (tenths(1) AND NOT tenths(0) AND NOT tenths(2) AND NOT tenths(3)); FDCPE_tenths_led3: FDCPE port map (tenths_led(3),tenths_led_D(3),clock,'0','0','1'); tenths_led_D(3) <= ((tenths(1) AND tenths(0) AND tenths(2) AND NOT tenths(3)) OR (NOT tenths(1) AND tenths(0) AND NOT tenths(2) AND NOT tenths(3)) OR (NOT tenths(1) AND NOT tenths(0) AND tenths(2) AND NOT tenths(3))); FDCPE_tenths_led4: FDCPE port map (tenths_led(4),tenths_led_D(4),clock,'0','0','1'); tenths_led_D(4) <= NOT (((tenths(1) AND NOT tenths(0) AND NOT tenths(3)) OR (NOT tenths(1) AND NOT tenths(0) AND NOT tenths(2)))); FDCPE_tenths_led5: FDCPE port map (tenths_led(5),tenths_led_D(5),clock,'0','0','1'); tenths_led_D(5) <= ((tenths(1) AND tenths(0) AND NOT tenths(3)) OR (tenths(1) AND NOT tenths(0) AND NOT tenths(2) AND NOT tenths(3)) OR (NOT tenths(1) AND tenths(0) AND NOT tenths(2) AND NOT tenths(3))); FDCPE_tenths_led6: FDCPE port map (tenths_led(6),tenths_led_D(6),clock,'0','0','1'); tenths_led_D(6) <= ((NOT tenths(1) AND NOT tenths(2) AND NOT tenths(3)) OR (tenths(1) AND tenths(0) AND tenths(2) AND NOT tenths(3))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C64A-5-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC2C64A-5-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 tens_led<2> 23 GND 2 tens_led<0> 24 tenths_led<1> 3 tens_led<3> 25 tenths_led<5> 4 tens_led<6> 26 tenths_led<6> 5 clock 27 tenths_led<3> 6 tens_led<1> 28 tenths_led<0> 7 tens_led<4> 29 ones_led<4> 8 tens_led<5> 30 TDO 9 tenths_led<2> 31 GND 10 GND 32 VCCIO-1.8 11 tenths_led<4> 33 ones_led<1> 12 KPR 34 ones_led<6> 13 VCCIO-1.8 35 ones_led<3> 14 KPR 36 reset 15 TDI 37 KPR 16 TMS 38 KPR 17 TCK 39 KPR 18 KPR 40 ones_led<0> 19 KPR 41 VCCAUX 20 KPR 42 ones_led<5> 21 VCC 43 ones_led<2> 22 KPR 44 startstop Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c*-*-* Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28